Acomparatoris a 1-bit ADC (seeFigure 6-44). If the input is above a threshold, the output has one logic value, below it has another. There is no ADC architecture which does not use at least one comparator of some sort. So while a 1-bit ADC is of very limited usefulness it is ...
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The comparator architecture is based on cut set algorithm which reduces the silicon area by time multiplexing many operations into single functional units. This type of algorithm reduces the power dissipation by eliminating unnecessary transitions. In addition, the comparator design is simple and ...
Comparator Logic Circuits Based on DNA Strand Displacement by DNA HairpinDNA computing is a hot research topic in recent years, molecular logic gate is an important foundation of DNA computer architecture and implementation. Local hairpin DNA chain substitution reaction ca...
de Sousa, P.B.M., Ramos, R.V.: Multiplayer quantum games and its application as access controller in architecture of quantum computers. Quantum Inf. Process. 7(2–3), 125–135 (2008) Article MathSciNet Google Scholar Fleischhauer, M., Imamoglu, A., Marangos, J.P.: Electromagnetically...
In this paper, a new design for a low power CMOS flash ADC is proposed. A 4 bit flash ADC with maximum acquisition speed of 2Gs/s, is implemented with 1.2V supply voltage. Hspice simulation result for proposed architecture verifying the analytical result is given. It shows that the ...
If the architecture supports virtual memory, an address translation unit may be included on... JP Moussouris,LM Crudele,SA Przybylski - US 被引量: 122发表: 1987年 Comparator bias: why comparisons must address genuine uncertainties. The article discusses the problem of comparator bias in ...
Figure 1: The proposed n-bit SAR ADC architecture2.1 Analysis of the Proposed Time-Domain ComparatorThe proposed time-domain comparator is illustrated in Fig. 2, which is composed of delay cells, two NAND gates, two D-flip-flop register based phase detector and a counter. The operation ...
Recently, computeraided design (CAD) tools have proved to be effective in VLSI design. A logic synthesis tool has been successfully realised that is able to synthesise a gate-level circuit from cells in the cell library using HDL (high-level description language) coding [6]. Most cell ...
Domestic Patent References: DE2725922B1N/A1978-12-21 Other References: Proceedings of the annual Symposium on Computer Architecture, University of Florida, 9.-11.Dec.1973, S.151-157 <- Previous Patent|Next Patent (Cleaning machine fee...) ->...