Then, HDP oxide layer was deposited and etched back again to form etch mask of a-Si exposed from nano-pillar tip, fol- lowed by a-Si wet etch, top angle As implantation and activation (Figure 2d,d*). After that, a nitride spacer was formed to protect the nano-pillar tips, and ...
hardmask layer in the recess, or forming the hardmask layer over the RMG electrode and tunnel oxide liners; forming, through the ILD over the drain, a first contact trench at least partially abutting the CT spacer or separated from the CT spacer by a block oxide liner; forming, through ...
indium-tin-oxide (ITO) transparent conductor 814 and with rubbed polyimide 812 (a surface coupling agent inducing homogeneous alignment), is then affixed to the die 802, at a distance of 4 μm to 10 μm, set by a mixture of optical adhesive (Norland 61) and precision glass fiber spacer...
Spacer 100 has a substantially uniform thickness and is put on one side of dynamic mask 108. Among other things, spacer 100 provides appropriate spacing between light source 112 and hologram 104 so that light source 112 is substantially at the focal point of the reflective hologram. Spacer 100 ...
The array 210 is held at a position separated from a surface where the optical sensors are arranged by a spacer 218 additionally provided with a function as a light beam baffle. By combining an opaque mask 216 on the array 210 with a perforated plate for diaphragming a visual field 240, ...
A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride
Following the formation of the spacer oxide 71a, 71b, 72a, 72b, the wafer periphery is covered with photoresist to form a bit line mask. The periphery of the memory array is not shown but is of well known configuration. Following the formation and patterning of the photoresist, arsenic is...
first tubular insulating spacer that is formed directly on a first cylindrical sidewall of the second metallic electrode layer and directly on a first cylindrical sidewall of the third metallic electrode layer. 16.The method of claim 15, further comprising:forming a dielectric hard mask layer over ...