This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in ...
This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in ...
Each memory cell array segment 109 includes a fuse circuit 105 which enables a respective first redundancy enable signal 51 when the column address is a redundancy address and enables a second redundancy enable signal 52, 53, 54, 55 for the memory cell array segment in which the redundancy occ...
The present invention provides a nonvolatile memory that can remove the defective column in the memory cell array. According to another aspect of the present invention, it is possible redundant column alternative, replace the column is removed. Both these processes are transparent to the outside, ...
The present invention relates to a column redundancy circuit in semiconductor memories which improves yields by means of substituting defective cells with redundant memory cells provided that defective memory cells are detected. The present invention of a redundancy circuit in semiconductor memories having ...
A high-speed redundancy circuit having redundant rows/blocks for replacing defective rows, columns and blocks. For row redundancy, an off-pitch encoder in conjunction with row control circuitry is used to disable defective rows while enabling non-defective rows. An off-pitch fuse is blown to enab...
Semiconductor memory device with redundancy circuits In a memory device, if there is a defective column among the memory cell columns in the memory cell array, all of the bit lines sharing the same I/O data lines as such a defective column are separated from the I/O data line regardless ...
A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capaci... R Omura,K Sugiura,T Komoike - US 被引量: 29发表:...
Column redundancy high area efficiency is flexible for non-volatile memory The present invention provides a nonvolatile memory that can remove the defective column in the memory cell array. According to another aspect of the present invention, it is possible redundant column alternative, replace the ...
Integrated circuit having memory array including ECC and column redundancy and method of operating same An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, ...