This project is to design yolo AI accelerator in verilog HDL. - HanPU-Code/CNN_YOLO_AI_accelerator
https://github.com/Haleski47/RTL-Implementation-of-Two-Layer-CNN https://github.com/Di5h3z/ECE-564-Convolutional-Neural-Network-Accelerator 具有详细设计的两层 CNN 详细的设计文档: https://github.com/Haleski47/RTL-Implementation-of-Two-Layer-CNN/blob/master/report/Apar%20Bansal%20ECE564%20Pro...
使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用. Contribute to wxdbb0/CNN-FPGA development by creating an account on GitHub.
SCHOUGAARD J H, LARSEN D E. A scalable and efficient convolutional neural network accelerator using...
SCHOUGAARD J H, LARSEN D E. A scalable and efficient convolutional neural network accelerator using...
中文: 这个git记录了我使用PYNQ实现CNN lenet5 加速的整个过程,主要包括如何将PYNQ移植到自定义的ZYNQ板子上,如何编写PL端的硬件加速器代码,包括HLS版本和Verilog版本,以及PS端的控制代码,PS端的控制代码主要使用python编写。 请大家继续关注,我会陆续更新这个git。 第一部分:移植PYNQ到Custom ZYNQ Board上 1.自定义...
GitHub repository:https://github.com/alexforencich/verilog-pcie Introduction Collection of PCI express related components. Includes PCIe to AXI and AXI lite bridges and a flexible, high-performance DMA subsystem. Currently supports operation with several FPGA families from Xilinx and Intel. Includes ...
SP-CNN A Scalable and Programmable CNN-based Accelerator.pdf update readme, add formula pic Apr 18, 2015 Template_library_v3.1.pdf template reference file add Mar 6, 2015 cnn_fpga_project_plan.pdf pure Verilog version, Schematic fail
The code is written by Verilog/SystemVerilog and Synthesized on Xilinx FPGA using Vivado. The code is just experimental for function, not full optimized. Architecture Only 4 elementary modules implemented: The conv, this module perform the convolution computing, the full connecting is also treated ...
加速器架构论文 Eyeriss系列论文例如《Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep ...