clocked flip-flop 英 [klɒkt flɪp flɒp] 美 [klɑːkt flɪp flɑːp]网络 时钟触发器; 时钟脉控的触发器; 时标触发器; 定时触发器
clocked flip flop 时标触发器,时控触发器 flip flop ring 触发计数环 height flip flop 高度双稳多谐振荡器,高度双稳态触发器,高度双稳态多谐振荡器 slave flip flop 从动双稳态触发器,自激多谐振荡器 signcontrol flip flop 符号触发器 d flip flop 【电】 D型正反器 buffered flip flop 【计】...
clocked flip-flop 英文clocked flip-flop 中文【电】 时钟跳摆
Thus to achieve a throughput of 100MB/sec, the data bus must be clocked at 50MHz. Timing: As mentioned above, data must be clocked at 50MHz, or every 20ns. In typical synchronous clocking designs, data is transmitted from the source and clocked at the receiver using a local clock signa...
5) clocked flip-flop 时钟触发器6) precise trigger timing 触发定时 1. By off line data analyzing, a precise trigger timing with resolution about 57ps has been gotten. 提出并研制了一种精密触发定时系统 。补充资料:触发器 触发器trigger 在外加信号下能转换工作状态的电路。通常用触发器的输出端...
A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and ...
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必应词典为您提供Clocked-Flip-Flop的释义,un. 定时触发器;时标触发器; 网络释义: 时钟器;时控触发器;时钟触发器;
A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and re...
6) unclocked flip-flop 无时钟触发器补充资料:变流器的触发电路 控制变流器中功率开关元件通断的电路。包括脉冲输出器和脉冲发生器两部分(见图)。根据控制信号的要求,脉冲发生器产生一定频率,一定宽度或一定相位的脉冲;脉冲输出器将此脉冲的电平放大为适合变流器中功率开关元件的驱动信号。 变流器的触发电路按控制的...