Sequential clock gating maximizes power savings at IP levelAnkur Krishnachanpreet singhKshitij BajajRitesh AgrawalSaurabh ShrimalIc Design Clock Gating Power Saving
The act of combinational clock gating does not change the functionality of the registers in the design, and hence, traditional logical equivalence checkers (LEC) can be used to verify the correctness of such clock gating transformations. Sequential clock gating, on the other hand, changes the seq...
SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR 优质文献 相似文献 参考文献 引证文献Maximum current estimation considering power gating As semiconductor technology scales down, the leakage power will soon become comparable to the dynamic power. To reduce both dynamic and leakage power, powe... F ...
Formal techniques are powerful, and sequential equivalence checking is a particularly appropriate way to apply them to check that a design will work the same way after a clock-gating strategy has been applied. However, the technique is not a magic wand, and needs to be applied with care and ...
To reduce clock power, which is a significant portion of the dynamic power consumed by a design, sequential clock gating is increasingly getting used over and above combinational clock gating. With the shrinking device sizes and increasingly complex designs, data is frequently transferred from one ...
United States Patent US6822478 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text
Model Checking Based Sequential Clock Gating (MCBCG) method formally proves particular sequential dependencies of registers on other registers and logic, thus sequentially gating such registers will not require further validation. An automation scheme for MCBCG methodology is also proposed in this paper....
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to...
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to...
Wu, "Clock-gating and its application to low power design of sequential circuits," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no... Q Wu,M Pedram,X Wu - IEEE Custom Integrated Circuits Conference 被引量: 542发表: 2000年 Clock-gating and its application to low powe...