cross-partition sector gates are not supported. resolution to work around this problem, change the clock enable typesetting in the clock control fpga ip parameter editor from distributed sector leveltoroot level and recompile . related products this article applies to 1 products show all need more...
[.../sources_1/bd/bd_hc/ip/bd_hc_xxv_ethernet_0/synth/bd_hc_xxv_ethernet_0_ooc.xdc:72] I'm using the xczu7eg-ffvf1517 part, that indeed doesn't have the referenced BUFGCTRLs. My project is in Vivado 2021.2. What can I do to eliminate those warnings?