告警解释 CLKMIB/4/CLOCKSOURCESWITCH: OID [oid] Clock source switch notification. (hwClockSrcSelChassisIndex = [integer],hwClockSrcSelType = [integer], hwClockChassisId = [integer], hwClockPllId = [integer], hwClockLastSourceName = [STRING], hwClockCurSourceName = [STRING], hwClockSourceSelMode...
告警解释 CLKMIB/4/CLOCKSOURCESWITCH: OID [oid] Clock source switch notification. (hwClockSrcSelChassisIndex = [integer],hwClockSrcSelType = [integer], hwClockChassisId = [integer], hwClockPllId = [integer], hwClockLastSourceName = [STRING], hwClockCurSourceName = [STRING], hwClockSourceSelMode...
hwClockSrcSelChassisIndex Indicates the index of the chassis where the clock source resides. hwClockSrcSelType Indicates the type of clock source selection. The value can be: System(0): system phase-locked loop sync2M-1(1): 2M phase-locked loop-1 sync2M-2(2): 2M phase-locked loop-2...
hwClockSrcSelChassisIndex Indicates the index of the chassis where the clock source resides. hwClockSrcSelType Indicates the type of clock source selection. The value can be: System(0): system phase-locked loop sync2M-1(1): 2M phase-locked loop-1 sync2M-2(2): 2M phase-locked loop-2...
/*=== 7、配置SPI使能模式 ===*/HSSPI.spi_reg->SLAVE_SEL_REG=0x01; /* 设置为手动设置...
const struct clk_mux_sel *inputs; struct { void __iomem *reg; u32 reg_shift; u32 reg_mask; } reg_data[REG_TYPE_NUM][REG_CONTROL_NUM]; struct list_head shared_bus_list; struct mutex mutex; spinlock_t spinlock; unsigned long rate; ...
type matrix is array(5 downto 0) of bit_vector(7 downto 0); type integer_vector is array(5 downto 0) of integer range 0 to 9; signal dig_a:matrix:=("11000000","11000000","11000000","11000000","11000000","11000000"); signal sel_t:bit_vector(5 downto 0):="111110"; ...
name = "sai_pll_ref_sel" }, }; #define CLK_GATE(gname, cname) \ { \ gname"_cg", \ IMX8MP_CLK_AUDIOMIX_##cname, \ { .fw_name = "ahb", .name = "ahb" }, NULL, 1, \ CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \ 1, IMX8MP_CLK_AUDIOMIX_##cname ...
SANDBOX_CLK_USDHC2_SEL, SANDBOX_CLK_I2C, SANDBOX_CLK_I2C_ROOT, }; enum sandbox_pllv3_type { @@ -74,4 +75,6 @@ static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg, width, 0); } int sandbox_clk_enable_count(struct clk *clk); #endif /* __SANDBOX...
failed to set parent of clk gpu3d_shader_sel to pll2_pfd2_396m: -22 sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms CPU identified as i.MX6DL, silicon rev 1.2 Console: colour dummy device 80x30 Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280) ...