摘要:针对先进智慧互联设备的全球领先讯号处理IP授权许可厂商CEVA公司发表新款CEVA-X2 DSP处理器,此小型的高效处理器解决方案专为LTE-Advanced Pro及5G智慧手机的多载波、多标準数据机设计中极为复杂的PHY控制任务而设计。CEVA-X2结合了强大DSP性能及有效的「控制」功能,包... 针对先进智慧互联设备的全球领先...
“特别值得注意的是,CEVA-X4——基于新型CEVA-X DSP架构的首款内核,由于具有强大的性能,可以在嵌入式系统中顺利运行CDNN(深层神经网络)。CDNN使得嵌入式系统执行深层学习任务的速度比基于GPU的领先系统提高3倍,同时消耗的功率减少30倍,所需存储带宽减少15倍。” CEVA市场营销及企业发展副总裁Eran Briman表示。 CEVA...
By working with CEVA and the HiPer Consortium, the SOC2 proves that reconfigurable computing is here with a DSP Instruction Set Architecture (ISA) that can be adapted to different workloads with custom hard-wired instructions that can be changed at any time in the future.” “Being part of ...
Other key features of SensPro include a memory architecture providing a bandwidth of 400GB per second, 4-way instruction cache, 2-way vector data cache, DMA, and queue and buffer managers for offloading the DSP from data transactions. SensPro is accompanied by an advanced set of software and ...
新型CEVA-X2 DSP實現高效的多重RAT PHY控制處理任務 2016年8月4日--針對先進智慧互聯設備的全球領先訊號處理IP授權許可廠商CEVA公司(NASDAQ: CEVA)今日發表新款CEVA-X2 DSP處理器,此小型的高效處理器解決方案專為LTE-Advanced Pro及5G智慧手機的多載波、多標準數據機設計中極為複雜的PHY控制任務而設計。
There was a flurry of press releases from Ceva today centered on the introduction of their new DSP architecture framework the XC4000. Ceva is excited about this core because of its power efficiency and that it utilizes an innovative instruction set to enable highly complex, soft...
是基于CEVA广为授权的Teaklite DSP核的第三代数字信号处理器架构。双MAC,32位处理的架构,总共10级的流水线使得其运行频率可以超过550MHz. CEVA-Teaklite-III是许多应用领域DSP的最佳选择,其中包括低成本的2G/2.5G/3G无线基带处理器,宽带语音及音频处理器,掌上型多媒体播放器,微机站,VOIP家用网关以及需要支持比如...
“DSP is an essential technology for processing complex audio and voice workloads and this initiative makes it easier for the RISC-V ecosystem to research, evaluate and eventually productize SoCs incorporating our best-in-class IPs.” “The availability of CEVA’s Audio DSPs and software IP for...
offering 4X the horsepower of the current CEVA-X2 DSP. The Instruction Set Architecture (ISA) supports Single Instruction Multiple Data (SIMD) widely used in neural network inference, noise reduction and echo cancellation, as well as native complex math and a range of floating-point options, in...
The latest core derived from the NEW CEVA-X architecture framework, the CEVA-X1 employs an extended Instruction Set Architecture (ISA) that, in addition to DSP processing, also allows it to efficiently handle CPU software workloads, such as protocol stack and system control. Comparing EEMBC® ...