R. S. Shen, J. B. Kuo, “Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique,” International Workshop on Power And Timing Modeling, Optimization and Simulation, LNCS 6951, pp. 143–151, 2011. :...
Spare cellState dependentleakage power and switching probabilityIn IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated ...
At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at least one normally functioning electronic components, the first conductive line and the second conductive line only during a rerouting process for reducing leakage power of the ...
Here in this paper Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology. 展开 关键词: Sub-threshold leakage reduction 6T-SRAM cell Leakage current and leakage power Proposed 6T 8T and 10T transistor models ...
The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDD_(min) of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of...
The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The FinFET approach and MTCMOS technique is used in 3T DRAM to compare the performance. At nano-scale FinFET is the su...
Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance...
Leakage power dissipation and stability continues to be a major concern in deep-submicron SRAM cell design. In this paper, a quasi-power-gating approach that reduces the leakage power dissipation in an SRAM cell while maintaining stability is proposed. As compared to a standard 6-transistor SRAM...
Integrated Three-Voltage-Booster DC-DC Converter to Achieve High Voltage Gain with Leakage-Energy Recycling for PV or Fuel-Cell Power Systems. Integrated three-voltage-booster DC-DC converter to achieve high voltage gain with leakage-energy recycling for PV or fuel-cell power systems. Energies .....
Low-Leakage, Low-Power, High-Stable SRAM Cell DesignLow-Leakage, Low-Power, High-Stable SRAM Cell DesignMOSFETTransmission gateSINMWTILeakage currentHold powerThis paper proposes a technique for designing low leakage stable SRAM cell, which can mitigate impact of Vt (threshold voltage) variation. ...