Decoder and timing control for 48CH 48 LAT SCLK SIN Line address for read Address decoder and writing control BANK_SEL 48kbit SRAM BANK A 16-bit x48CH x 32/16 Line BANK B 16-bit x48CH x 32/16 Line Vsync 48 WRTGS Vsync Command Decoder WRTFC Thermal Pad GND READFC1/2 READSID ...
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(GS) data latch XRST Address Counter ADR Select LAT16B LOAD LAT768B 0 LAT Command Decoder SCLK SCLKB LATFC XRST XRFESH Poker Trans Mode 2 Power On Reset XRST PRIODEND 3 2 XRFRESH GCLK EDGE 16 bit GS Counter 34 48 bit Common Shift Register 47 48 SEL_TD0 48 LSB 48 48 48 GS ...