Computer Science - Networking and Internet ArchitectureBuffering architectures and policies for their efficient management constitute one of the core ingredients of a network architecture. In this work we introduce a new specification language, BASEL, that allows to express virtual buffering architectures ...
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A local rise in [K]causes potassium ions to enter glial cells, which have membranes that are highly permeable to K; potassium then leaves the glial cells at other locations where [K]has not risen. We report here the first study of the individual ion channels mediating potassium buffering by...
This question is off topic in this newsgroup. A larger buffer in the streaming application will improve performance as there will be less impact of the delay variations in the network. Sandeep -- http://www.EventHelix.com/EventStudio EventStudio 2.0 - System Architecture Design CASE Tool Jul...
K Flautner - 《Proc.of Int.symp on Computer Architecture May》 被引量: 1215发表: 2002年 Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip...
An integrated circuit (IC) module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Multi-Chip Module (MCM), includes a buffering IC that buffers clock and other in
A buffer model in an HTTP streaming client may include receiving a first content fragment of a first content stream in response to a first HTTP request. It may also include receivin
In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the ...
The implementation of a low-latency optical packet switch architecture that is controllable while scaling to over thousand ports is investigated in this paper. Optical packet switches with thousand of input/output ports are promising dev... HJS Dorren - Proceedings of the 16th Annual Symposium of ...
10.The computer program product of claim 7, wherein the delta wire delay is increase in stage delay when the noise impact on timing of the net is taken into account. 11.An apparatus comprising:a processor; anda memory coupled to the processor, wherein the memory comprises instructions which...