In this work, we prevent a processor from flushing the pipeline even under branch misprediction by allowing the instruction fetcher to work continuously. To this end, we propose a fast and low-cost branch recovery scheme using the incremental register renaming and the bit-vector based rename map...
The fetch addresses used by the processor are coupled to the branch address tags. If a hit occurs, the instruction at the fetch address causing the hit is presumed to be a previously encountered branch. The history information is accessed and a prediction on the direction of the branch is ma...
Chuang, et al., "Predicate Prediction for Efficient Out-of-order Execution", 2003, ICS '03 Proceedings of the 17th annual international conference on Supercomputing, pp. 183-192. Gochman et al., "The Intel Pentium® M Processor: Microarchitecrure and Performance", May 21, 2003, Intel Te...