5outputout_or_logical,6output[5:0] out_not7);8assignout_or_bitwise=a|b;9assignout_or_logical=(a>0)|(b>0);//逻辑或和按位或这两个的区别还待记牢10assignout_not= {~b,~a};//verilog中的拼接语法,每一个部分有三个量,拼接之后为6个,故为[5:0]11endmodule...
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location. Americas América Latina(Español) Canada(English) United States(English) Europe Belgium(English) ...