I've now got a tristate buffer at the SRAM side and one at the GPIO side and 'split' the internal database bus into a read direction bus and a write direction bus (seemed simpler than trying to get a bidirectional bus internally). So, that's OK and makes sense. Now my problem ...
DescriptionDue to a problem in the Quartus® II software versions 14.1 and earlier you may see functional problems if you connect the data port of a bidirectional pin to a constant zero in your design as the OE and IN ports for the bidirectional buffer may be switched. Resolution Use the ...
may be used to avoid data hazards. The write data to be transmitted to the device may be temporarily stored in the buffer and, if a read to a location in the device corresponding to the write data occurs during the retry remedial action, the write data may be obtained from the buffer....
I've now got a tristate buffer at the SRAM side and one at the GPIO side and 'split' the internal database bus into a read direction bus and a write direction bus (seemed simpler than trying to get a bidirectional bus internally). So, that's OK and makes sense. Now my problem...
I've now got a tristate buffer at the SRAM side and one at the GPIO side and 'split' the internal database bus into a read direction bus and a write direction bus (seemed simpler than trying to get a bidirectional bus internally). So, that's OK and makes sense. Now my problem...