tPLH = tPHLWIDE OPERATING VOLTAGE RANGE.M1R C1RVCC (OPR) = 2 V TO 6 V (Micro Package) (Chip Carrier)PIN AND FUNCTION COMPATIBLE ORDER CODES :WITH 54/74LS42 M54HC42F1R M74HC42M1RM74HC42B1R M74HC42C1RDESCRIPTIONThe M54/74HC42 is a high speed CMOS BCD-TO-DECIMAL DECODER ...
October 1987 Revised January 1999 CD4028BC BCD-to-Decimal Decoder General Description The CD4028BC is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A, B, C, and D, results in a...
功能: Decoder/Driver 高度: 4.57 mm 长度: 19.3 mm 电路数量: Quad 工作温度范围: 0 C to + 70 C 系列: SN74145 宽度: 6.35 mm 逻辑类型: Decoders/Drivers 电源电流—最大值: 7 mA 高电平输出电流: - 20 mA 低电平输出电流: 80 mA 最大时钟频率: 75 MHz 工作电源电压:...
116Kb/4PBCD-to-Decimal Decoder MM54C42 107Kb/4PBCD-to-Decimal Decoder Fairchild SemiconductorDM7442A 41Kb/4PBCD to Decimal Decoder CD4028BC 76Kb/6PBCD-to-Decimal Decoder Nexperia B.V. All right...HEF4028B 209Kb/10PBCD to decimal decoder ...
CD4028BCN 53Kb / 6P BCD-to-Decimal Decoder More results 类似说明 - CD4028BC 制造商 部件名 数据表 功能描述 Hitachi Semiconductor HD74LS42 61Kb / 6P BCD-to-Decimal Decoder Toshiba Semiconductor TC4028BP 223Kb / 5P BCD - TO -DECIMAL DECODER Fairchild Semiconductor CD4028BC 53Kb / 6P...
A BCD-to-decimal decoder has ___ data input lines and ___ data output lines.A.1,10B.10,10C.7,9D.4, 10的答案是什么.用刷刷题APP,拍照搜索答疑.刷刷题(shuashuati.com)是专业的大学职业搜题找答案,刷题练习的工具.一键将文档转化为在线题库手机刷题,以提高学
Ascii85 Decoder UTF8 Encoder UTF8 Decoder UTF16 Encoder UTF16 Decoder Uuencoder Uudecoder Morse Code Encoder Morse Code Decoder XOR Encryptor XOR Decryptor AES Encryptor AES Decryptor RC4 Encryptor RC4 Decryptor DES Encryptor DES Decryptor Triple DES Encryptor ...
Base58 Decoder Ascii85 Encoder Ascii85 Decoder UTF8 Encoder UTF8 Decoder UTF16 Encoder UTF16 Decoder Uuencoder Uudecoder Morse Code Encoder Morse Code Decoder XOR Encryptor XOR Decryptor AES Encryptor AES Decryptor RC4 Encryptor RC4 Decryptor
MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, BCD-TO-DECIMAL DECODER, MONOLITHIC SILICON (SUPERSEDING DESC 5962-86821B)doi:MIL DSCC 5962-86821C
The arrangement includes a BCD to decimal decoder circuit. The display involves first removing the base number 6 from each decimal location by subtraction. Alternative arrangement involve BCD plus 6 to decimal decoder circuits and a mixture of BCD to decimal and BCD plus 6 to decimal decoder ...