parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output parameter BIT_COUNT_WIDTH_PP = 4; // Width of bit counter // I/O declarations input clk_i; // clock signal input ce_i; // clock enable input input rst_i; // synchronous reset input start_i; // initiates a conve...
/* Synchronous Logic for registering the data and incrementing the counter for binary data */ always @ (posedge clk or negedge rstn) begin if (!rstn) begin counter_binary_reg <= 'b0; counter_gray_reg <= 'b0; end else begin counter_binary_reg <= counter_binary + 1; counter_gray_reg...