设计一种新的CDR技术,使用分数分频器(Fractional Divider)和背景ECA来优化采样相位并最大化垂直眼形间隔(Vertical Eye Margin, VEM)。 该技术通过在全局锁相环(Phase Locked Loop, PLL)附近放置一个由CDR控制的分数分频器来补偿频率偏移,从而减少功耗并避免使用相位插值器。 文章的创新点: 利用低功耗的全球时钟分配...
In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver...
A novel equal-slope baud rate clock and data recovery (CDR) algorithm is proposed. By positioning the locked point on pulse response where pre-cursor slope and main-cursor slope are equal, an optimized eye-opening is achieved with enhanced eye height, eye width and timing margin. The algorith...
The baud-rate CDR reduces the burden of multi-phase clock generation and distribution, thus reducing the power consumption of clocking circuits. A pattern-based phase detector (PBPD) is proposed in the clock recovery path to address the transition density (TD) reduction caused by the baud-rate...
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS and consumes 78 mW from a 0.95 V supply when operating at 11.8 Gb/s. F Spagna,L Chen,M Deshpande,... - Solid-state Circuits Conference Digest of Technical Papers 被引量: 83发表: 2010...
{1}.DFECDR.Phase;%Get DFE tap valuestapsBangBang = systemBangBang.Wave.outparams{1}.DFECDR.TapWeights;%Calculate hula hoop indices and voltagesndx_BangBang = phase_BangBang*SamplesPerSymbol; ndx_BangBangHoop = ndx_BangBang + [-0.5 0.5]*SamplesPerSymbol; v_BangBangHoop = interp1(ndx_k,...
In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver...
CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance ...
This work focuses on the practical aspects of high speed baud-rate clock and data recovery (CDR). Baud-rate CDRs reduce the number of clock sampling phases compared to edge-sample phase detector (PD) based CDRs. These CDRs do not require transition samples in addition to the data samples...
Finally, a digital clock/data recovery (CDR) circuit is presented, which includes a demultiplexer (DeMUX) with a short delay time to reduce the loop ... JE Lin,SI Liu - 《IEEE Transactions on Very Large Scale Integration Systems》 被引量: 0发表: 0年 A novel bit serial computing scheme...