读取端的控制信号同理。 参考资料:https://www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf 以下是仿真代码 `timescale1 us / 1 psmoduledata_fifo_wrapper (M_AXIS_tdata, M_AXIS_tkeep, M_AXIS_tlast, M_AXIS_tvalid, S_AXIS_tready, axis...
so I kept the subset coverter between the core output and my AXIS interconnect to insert it (otherwise, it's not present when I expand the bus on the interconnect), then wired in a constant on the switch so that this particular path should always redirect. Thing...