On my design i have a memory mapped AXI bus that is controlled from an AXI master (PCIe) that receives its transactions from a host PC. My idea is the be able to send PROM bistream over the PCIe link, to the AXI Quad SPI IP Core that programs the SPI ...
I want to use 2 AXI-QUAD SPI IP modules in vivado block design as per my hardware. I am using xc7a200tffg1156-1. I have added 2 spi IP modules and conneted all signals but while placing pins i am getting an error like below "[Place 30-99] Placer failed with error: 'There are...