MI_DATA_WIDTH SI_ID_WIDTH FIFO_MODE ACLK_ASYNC SYNCHRONIZATION_STAGESFixed clocks (MHz)Clock InputFmax (MHz)LUTsFFsDSPs36k BRAMs18k BRAMsSpeedfile Status xc7a200t fbg676 2 downsize1024_7a2 AXI4 READ_WRITE 1024 512 4 none s_axi_aclk 172 1436 1736 0 0 0 PRODUCTION 1.23 2018-06-13 xc7...
(Inserts the data width converter) Now, in the actual c code running on the embedded Arm, to read the full 64 bits do I need two read statements or does the AXI bus somehow know that it must transfer two 32 bit values? If two read statements are ne...