always @(posedge clk_i)beginif(!rst_n_i)_send_data <= {Num_bit{1'b0}};elseif(state == S_START) _send_data <=_send_data_t;else_send_data <= _send_data; end 这里的数据线序需要理一下,因为发送按tx_reg <= _send_data[cn\\t_bit];输出,所以_send_data的最高位是奇偶校验位最...
localparam time TestTime =8ns;typedeflogic [7:0]byte_t;typedeflogic [AxiAddrWidth-1:0]axi_addr_t;typedeflogic [AxiDataWidth-1:0]axi_data_t;typedeflogic [AxiStrbWidth-1:0]axi_strb_t;//simulation address rangelocalparamaxi_addr_tStartAddr =axi_addr_t'(0); localparamaxi_addr_tEndAddr=...
AXI_lite是轻量级的AXI协议,它每次传输的数据和地址的突发长度只有1,也就是burst=1。常用与较少数据量的存储映射通信,比如配置寄存器。 下面把AXI_lite的所有信号罗列出来: 写地址 AW_ADDR ADDR_WIDTH-1 :0 AW_VALID AW_READY AW_PORT 1 : 0 写通道保护信号 写数据 W_DATA DATA_WIDTH-1 : 0 W_...
reg[M_AXI_ADDR_WIDTH-1:0] axi_awaddr =0;//AXI4 写地址 regaxi_awvalid =1'b0;//AXI4 写地有效 wire[M_AXI_DATA_WIDTH-1:0] axi_wdata ;//AXI4 写数据 wireaxi_wlast ;//AXI4 写LAST信号 regaxi_wvalid =1'b0;//AXI4 写数据有效 wirew_next= (M_AXI_WVALID & M_AXI_WREADY);...
always @(posedge M_AXI_ACLK) beginif (M_AXI_ARESETN == 1'b0) beginM_AXI_ARADDR <= C_M_TARGET_SLAVE_BASE_ADDR; // 初始值为基地址endelse if (M_AXI_RLAST) beginM_AXI_ARADDR <= M_AXI_ARADDR + (C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH / 8); // 每次读完后，跳过已经...
简单的depth-1 FIFO实现 使用depth-1 FIFO传输数据,可以这样设计: // Depth 1 FIFO. always @(posedge CLK)begin if(RESET) begin fifo_line_valid <= 0; fifo_push_ready <= 1'b0; fifo_data <= {WIDTH{1'b0}}; end else begin fifo_push_ready <= fifo_pop_ready; if (fifo_push_ready) be...
module myip_v1_0_S00_AXI # ( // Users to add parameters here // User parameters ends // Do not modify the parameters beyond this line // Width of S_AXI data bus parameter integer C_S_AXI_DATA_WIDTH = 32, // Width of S_AXI address bus ...
1:axi-lite-slave的axi_awready always@(posedgeS_AXI_ACLK ) begin if( S_AXI_ARESETN ==1'b0) begin axi_awready <=1'b0; aw_en <=1'b1; end else begin if(~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en) begin ...
input wire [DATA_WIDTH-1:0] fpga2dram_data,//数据发送到dram input wire fpga2dram_valid,//有效信号 input wire fpga2dram_start, //开始信号,比valid信号提前几个周期,用于配置写到dram的地址等 /// dram 2 fpga output wire [DATA_WIDTH-1:0] dram2fpga_data,//数据从dram来 ...
pwm_led_ip_v1_0.v 1 `timescale 1 ns / 1 ps 2 3 module pwm_led_ip_v1_0_S00_AXI # 4 ( 5 // Users to add parameters here 6 parameter FREQ_STEP = 10'd100, 7 // User parameters ends 8 // Do not modify the parameters beyond this line 9 10 // Width of S_AXI data bus...