asicfpgavhdledartlverilogcsrsystemverilogsocuvmralaxiambaapbregister-descriptionswishbone-busuvm-ral-modeluvm-register-modelwiki-documents UpdatedFeb 19, 2025 Ruby ZipCPU/sdspi Star278 Code Issues Pull requests SD-Card controller, using either SPI, SDIO, or eMMC interfaces ...
Ø 一个NVMe A4S Host Controller IP直接连接到PCIe SSD Ø 易于集成的同步、可综合Verilog设计 Ø 通过完全验证的NVMe A4S Host Controller IP 2 概述 NVMe A4S Host Controller IP作为一个对PCIe SSD的高性能存储控制器,不但提供对PCIe SSD的配置管理功能,而且提供对PCIe SSD的IO(Page)读写以及DMA读写...
Audio controller (I2S, SPDIF, DAC) audiofpgaverilogdaci2saxi4-litespdif UpdatedSep 1, 2019 Verilog USB -> AXI Debug Bridge fpgausbverilogusb-cdcaxi4-lite UpdatedJun 5, 2021 Verilog ic-lab-duth/NoCpad Star33 Code Issues Pull requests ...
在Vivado2019.1中,调用AXI BRAM Controller (4.1)IP核。 设置Memory Depth 为262144。 BRAM Instance 选择Internal。 tb_axi_bram.v `timescale1ns/1ps// Company:// Engineer:/// Create Date: 2020/12/22// Author Name: Sniper// Module Name: tb_axi_bram// Project Name:// Target Devices:// Tool...
Code Issues Pull requests Basic USB 1.1 Host Controller for small FPGAs fpga usb usb-host axi4-lite ulpi utmi Updated Jun 6, 2020 C ultraembedded / core_audio Sponsor Star 74 Code Issues Pull requests Audio controller (I2S, SPDIF, DAC) audio fpga verilog dac i2s axi4-lite spdif...