(afteraccessingVFregisters).ForIntel-definedVSECaccess,yourapplicationneedstoprogramtheVSECfield(0x14068bit[0])first.ThenallaccessesfromtheuserAvalon-MMinterfacestartingatoffset0xD00istranslatedtoVSECconfigurationspaceregisters.®®SendFeedbackF-TileAvalonStreamingIntelFPGAIPforPCIExpress*UserGuide...
cannot be set to 0xFFFF per the PCI Express Base Specification. continued... L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization(SR-IOV) Intel® FPGA IP for PCI Express* User Guide 34 Send Feedback 4. Parameters683111| 2024.09.12 Register Name Device ID VF ...