simple-audio-card,dai-link@2 { format = "left_j"; bitclock-master = <&mic_cpu>; frame-master = <&mic_cpu>; mclk-fs = <512>; mic_cpu: cpu { sound-dai = <&sai0>; clocks = <&mclkout0_lpcg 0>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; }; pcm3168_adc...
你这里设置没有问题的,是这样你不播放音频的话是不会有时钟输出的。你这里播放音频的时候再测一下,应该就是有的了。
model = "wm8960-audio"; cpu-dai = <&sai2>; audio-codec = <&codec>; asrc-controller = <&asrc>; codec-master; gpr = <&gpr 4 0x100000 0x100000>; /* This is SAI2_MCLK setting in GPR register */ /* * hp-det = <hp-det-pin hp-det-polarity>; * hp-det-pin: JD1 JD2 or...
I used AIC3204EVM-K and disconnect MCKL from TAS1020. And I conntect BCLK to MCLK. It works, but the suound quality is not good enough. I am trying to fine turn PLL, but notthing be changed. Do you have any good idea for it? Thanks! PS. Defaule setting. (MCLK = 11.2896MHz, ...
, When the MCLK of the TAS5731M is absent or out of range, the device uses an internal oscillator to produce the internal clock and mutes the outputs until a proper MCLK is provided. Best Regards, -Diego Meléndez López Audio Applications Engineer...
Errata 1 PLL Audio Clock (MCLK1, MCLK2) Generation Bug 1.1 Description • When using the divide-by-four mode, there is a potential for the PLL to generate an incorrect clock (MCLK1 and/or MCLK2). • When using the divide-by-three mode, a 50% duty cycle of the divided clock (...
However, it is written in ELECTRICAL CHARACTERISTICS (page 2, both DS) that maximum MCLK freq. id DSD mode is 11.3MHz, it is not clear - in PCM mode MCLK can be up to 73.7MHz (for some bitrates) and it is also used for control interface. ...
When I set the PLL CLKIN DIVIDER register address 0x0F with PLL_CLKIN = Input from BCLK, I get worse audio quality. It's as if the audio has low voice, but high gain, where it's almost as if there's white noise coming through the speaker. When I change back to using MCLK, th...
What are the requirements for the MCLK clock signal input to the TLV320ADC5140, TLV320ADC3140, and TLV320ADC6140 when operating as an Audio master with an external MCLK input? 5 年多前 Collin Wells5 年多前 TI__Guru63185points 1.) The maximum input frequency is: 36.864MHz. ...
Is it safe to run the device with a slightly slower rising MCLK or do I have to re-check my layout or should that 5nSec from the spec rather read as a minimum time? Thanks in advance Hi, Andreas, Welcome to E2E, Thanks for your interest in our products!. ...