1.at speed test structure and OCC Controller 2.OCC Controller 当使用set_dft_configuration -clock_controller enable运行insert_dft DFT编译器会将DFT_clk_mux和DFT_clk_chain组件添加到网表中。 2.1OCC Controller的结构 ①fast pulse controller ②clock selection circuit DFT_clk_mux I/O ports 2.2 OCC脚本...
design_name occ_clock_mux -pllclocks [pll/clk1 pll/clk2] -ateclocks [ate_clock] -cycles_per_clock 2 • scan_configuration 的设置 2.OCC 已经存在 这种情况下由于 OCC 已经插入,因此命令 set_dft_clock_controller 在这里已经 没有意义了,这里需要让 DFT 知道 occ 输出时钟信号的属性,使用的方法...
为了支持 at - speed 测试 ,需要 在 CRG和模块之间加入 OCC 电路。 OCC电路可以支持以下功能 : ·正常功能模式下输出系统时钟 。 ·stuck _ at 测试模式下输出测试机慢速时钟 scan_clk。 ·at_ speed 测试模式下输出如图 2 的时钟。 OCC电路的模块结构示意图如图 3 所示。 图 3 OCC的结构示意图 下面分别...
OCC controller,and then,the test pattern is generated by automatic test pattern generation(ATPG) tools.Next,the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified.The result shows that the design of an at-speed scan test in this paper is...
This paper attempts to quantify the economic benefits of including improved design for test (DFT) strategies into the ASIC design process. The qualitative ... R Gayle - IEEE International Test Conference on Designing 被引量: 48发表: 1993年 Clock controller for at-speed testing of scan circuits...
A new circuit for at-speed scan SoC testing using an at-speed testing method.In this paper,an on-chip clock(OCC) controller with a bypass function based on an internal phase-locked loop is ... 林伟,施文龙 - 《Journal of Semiconductors》 被引量: 1发表: 2013年 SYSTEM-ON-CHIP FOR AT-...
In ATPG mode, the on chip controller is used for generating capture clocks along with scan shift clocks. There are different paths inside the OCC for generating capture clock or shift clock. Shift clock is used for scan load and unload while transition faults are covered by two at speed capt...