design_name occ_clock_mux -pllclocks [pll/clk1 pll/clk2] -ateclocks [ate_clock] -cycles_per_clock 2 • scan_configuration 的设置 2.OCC 已经存在 这种情况下由于 OCC 已经插入,因此命令 set_dft_clock_controller 在这里已经 没有意义了,这里需要让 DFT 知道 occ 输出时钟信号的属性,使用的方法...
OCC controller,and then,the test pattern is generated by automatic test pattern generation(ATPG) tools.Next,the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified.The result shows that the design of an at-speed scan test in this paper is...
1.at speed test structure and OCC Controller 2.OCC Controller 当使用set_dft_configuration -clock_controller enable运行insert_dft DFT编译器会将DFT_clk_mux和DFT_clk_chain组件添加到网表中。 2.1OCC Controller的结构 ①fast pulse controller ②clock selection circuit DFT_clk_mux I/O ports 2.2 OCC脚本...
scan enable at 1), where each OCC was being initialized and the Pattern was loaded using the relatively slow external ATE clock, according to an embodiment, where the internal fastest clock signals are propagated in a predictable pulse range to initialize the OCCs (for example, 3 OCC are sho...
using an at-speed testing method.In this paper,an on-chip clock(OCC) controller with a bypass function based on an internal phase-locked loop is ... 林伟,施文龙 - 《半导体学报》 被引量: 1发表: 2013年 At-Speed Scan Test in ASIC Design with On-Chip Clock With the gradual improvement ...