C. J. Clark, “iMajik: Making 1149 1 TAPs disappear and reappear in SoCs and 3D packages,” 2010 28th VLSI Test Symposium (VTS), Santa Cruz, CA, 201 0, pp. 117-122. Zhu Min, Yang Chunling and Peng NZhang, “Design of IEEE1149.1 testing bus controller IP core,” 2009 4th IEEE...
芯片达到设计性能要求因此测试必须覆盖与速度相关的缺陷而这同时面对芯片不断提高的性能往往需要更高测试频率的测试设备测试成本的增加对芯片制造成本的控制的压力也越来越大为此必须对过去的测试策略进行检讨以适应现代soc设计的挑战 atSOC 设计中的 at-speed ATPG 摘要:SOC(片上系统集成)已成为 VLSI(超大规模集成电路...
At-speed testing is becoming crucial for modern VLSI systems which operate at clock speeds of hundreds of megahertz to several gigahertz. In a scan-based test methodology, it is common to use transition delay fault model for at-speed testing. The test procedure is to create a transition at ...
Vorisek, V., et al., “Improved Handling of False and Multicycle Paths in ATPG,”Proceedings of the 24th IEEE VLSI Test Symposium (VTS 06), IEEE Computer Society Press. Linn, X., et al., “Timing-Aware ATPG: A Novel Test Generation Method for High-Quality At-speed Test,” ATS 2006...
Interconnect defects such as weak resistive opens, shorts and bridges increases the path delay affected by a pattern during manufacturing test but not significant enough to cause a failure at functional frequency. Faster-than-at-speed te... TW Chen - 《Proc IEEE Vlsi Test Symp》 被引量: 11发...
Delay fault testing for VLSI circuits. circuits with significant reduction in the number of faults.; Testing delay defects requires application of test vectors at the rated speed of the circuit... A Krstic - University of California, Santa Barbara. 被引量: 0发表: 1998年 加载更多来源...
The push for higher performance at lower power and cost has driven the VLSI industry towards System-on-Chip (SoC) integration resulting in designs with multiple clocks. It is common to see blocks that share the same clock source having synchronous interactions when the frequency relation is an ...
In this paper we present a Design-For-Test (DFT) technique implemented on a high speed VLSI device that allows us to use a low speed/cost tester to perform at-speed scan transition and path delay testing. The concept is to:-• Use an i... EH Freescale,CD Renfrew,RG Freescale 被引...
Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays(Special Issue on Test and Diagnosis of VLSI) Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the... BOATENG,Kwame,Ose...
Speed-path debug techniques based on at-speed scan test patterns. Potential speed paths are identified based upon detected at-speed scan pattern failures and unknown X-value simulat