last_shift launch mode (低速测试) system_clock launch mode ( launch on capture) 1.at speed test structure and OCC Controller 2.OCC Controller 当使用set_dft_configuration -clock_controller enable运行insert_dft DFT编译器会将DFT_clk_mux和DFT_clk_chain组件添加到网表中。 2.1OCC Controller的结构 ①...
As the electronic design automation (EDA) industry focuses on design-for-manufacturability (DFM), the older problem of design-for-test has almost been forgotten. But ICs built at 90 nanometers and below pose new and com-plex challenges for design-for-testability (DFT) tools and techniques. ...
Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. Designers will se...
The pin overhead problem of nonscan design for testability (DFT) and built-in self-test design has been an unsolved problem for a long time. A new algorithm is proposed to connect extra pins of control test points with primary inputs. An economical test point structure is introduced, in ...
It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This article proposes a new design-for-testability (DFT) scheme for launch...
This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertzmicroprocessor with multi-clock domains. Thepresented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compre...
In this paper we present a Design-For-Test (DFT) technique implemented on a high speed VLSI device that allows us to use a low speed/cost tester to perform at-speed scan transition and path delay testing. The concept is to:-• Use an i... EH Freescale,CD Renfrew,RG Freescale 被引...
Double-capture技术是另一种at-speed test的技术,是一种true at-speed test,可以测试所有的intra-clock-domain和inter-clock-domain的structural faults和delay faults,无论是在synchronous 或asynchronous design。并且scan enable比较容易physical implementation,scan/ATPG也容易实现。
This paper attempts to quantify the economic benefits of including improved design for test (DFT) strategies into the ASIC design process. The qualitative ... R Gayle - IEEE International Test Conference on Designing 被引量: 48发表: 1993年 A Capture-Safe Test Generation Scheme for At-Speed Sca...
如果不同的时钟域之间有确定的相位关系和 时序要求, 也可进行时钟域之间的”at-speed”的测试.同样的芯片设计,Fastscan 一般可以提供较高的 测试覆盖率以保证测试质量; 同时, Fastscan 在测试向量压缩方面效果最好; 而且其运行时间也比其他 ATPG 工具要快上数倍。 · 设计师开始 SOC 设计时, 必须对 DFT 给予...