Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.Inventores Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel ...
At-speed scan testing 优质文献 相似文献 参考文献 引证文献Low-capture-power test generation for scan-based at-speed testing Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being sev... X Wen,Y ...
3.scanmasterclock & masterclock 对于多路复用触发器(Mux-D),ScanClock的信号“type”是用于指定ScanMasterClock(扫描移位时钟)和MasterClock(捕获时钟)。 用于Mux-D扫描设计,同一时钟通常用于移位和捕获。 当定义了Scanclock并report_dft_signal,将同时看到ScanMasterClock和MasterClock属性。 set_dft_signal -view exis...
Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded...
摘要: The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite....
2.5 Definition of at-speed scan test In contrast to running the chip at application speed, at- speed testing means that the time between launch event and capture event is one application period apart (see Fig. 7 in Section 5). The clock period of the test program does not necessarily ...
前面提到了OCC电路要支持一个正常工作模式和Stuck—at和at_speed2种测试模式。在正常工作模式(Test—mode=0)下要输出Func_clk。在at—speed模式下受scan_enable控制输出Scan-clk和launch、capture两个脉冲。此时只要把示意图中的testmode信号分解为at.._speedjestmode和stuck-at-testmode两种模式,用来选中所需的scan...
Double-capture技术是另一种at-speed test的技术,是一种true at-speed test,可以测试所有的intra-clock-domain和inter-clock-domain的structural faults和delay faults,无论是在synchronous 或asynchronous design。并且scan enable比较容易physical implementation,scan/ATPG也容易实现。
At-Speed Scan Transition and Path Delay Testing Using On-chip PLL for High Frequency Device and Low Frequency Tester In this paper we present a Design-For-Test (DFT) technique implemented on a high speed VLSI device that allows us to use a low speed/cost tester to perform... E Haioun,...
专利名称:Combinatorial at-speed scan testing 发明人:Atul S. Athavale,Jason R. Ng 申请号:US111664 32 申请日:20050623 公开号:US0726674 3B 2 公开日:20070904 专利附图: 摘要:A processor including a first distributed shift generator associated with a first time domain, wherein the first ...