We propose a methodology, based on model checking, to verify the process of controller synthesis. An extensive collection of control-flow properties for a synthesized RTL design is identified. These properties are then formulated in Computation Tree Logic and verified against a formal model of the ...
Pointner, S.; Frank, O.; Hazott, C.; Wille, R. Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows. In Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, FL, USA, 15–17 July 2019; IEEE: Piscataway, NJ, ...