This volume deals with machines which are explictly parallel in nature and concentrates on the architecture of systems in which a number of processors operate in concert to achieve high performance. It represents an historical progression describing some recently evolved machines. Computer Systems ...
Land Grid Array (LGA) is a type of electronic packaging technology used in computer processors and other high-performance integrated circuits. LGA technology offers several advantages over older packaging technologies, including higher pin density, impro
RISC array processors such as those based on the Epiphany architecture may offer significant computational power efficiency in the near future with requirements in increased core counts, including long-term plans for exascale platforms. The power efficiency of the Epiphany architecture has been specificall...
sequential logic. They can also implement multilevel logic functions, whereas PLAs can implement only two-level logic. Modern FPGAs integrate other useful features, such as built-in multipliers, high-speed I/Os,data convertersincluding analog-to-digital converters, largeRAMarrays, and processors. ...
The associative linear array processor (ALAP) is a new approach to making large associative processors practical. Data storage in shift registers, bit-seri... CA Finnila,HH Love - 《IEEE Trans Computer》 被引量: 46发表: 1977年 Low-level vision using an array processor Most low-level vision...
A systematical method of stopping the processors, diagnosing the faulty elements, and reconfiguring the array is devised. A switch structure is introduced for the reconfiguration of mesh-connected arrays. This architecture offers great flexibility in structuring the array. Errors are detected at run-...
In this paper we demonstrate the applicability of a simple memory array architecture to some intermediate-level computer vision tasks. This architecture, called theAccess Constrained Memory Array Architecture (ACMAA) has a linear array of processors which concurrently access distinct rows or columns of...
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single
As the result of wiring, in our system, symmetric replicatable elements, are wired together for sharing interconnection paths. SIMD A processor array architecture wherein all processors in the array are commanded from a Single Instruction stream, to execute Multiple Data streams located one per ...
The BOPS(R) ManArray/sup TM/ architecture is presented as a scalable DAP platform for the embedded processor domain. In this domain, ManArray-based processors use a single architecture definition, that supports multiple configurations of processing elements (PEs) from low end single PE to large ...