Owens, "Area-time-power tradeoffs in parallel adders," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 689-702, Oct. 1996.Chetana Nagendra et al., Area-Time-Power Tradeoffs in Parallel Adders, Oct. 1996, IEEE Transactions on Circuits and Systems-...
13th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation PATMOS 2003; Sep 10-12, 2003; Turin, ItalyJoao Loenardo Fragoso, Gilles Sicard, and Marc Renaudin. Power/area tradeoffs in 1-of-M parallel-prefix asynchronous adders. In ...
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: ProceedingsJoao Loenardo Fragoso, Gilles Sicard, and Marc Renaudin. Power/area tradeoffs in 1-of-M parallel-prefix asynchronous adders. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing ...