(i.e., not just a paragraph) in the Nios II HW development tutorial that tells the reader to change this setting before starting Quartus compilation. The revised tutorial is up on our web site and will ship on the Nios II CDs shortly. Jesse Kempa Altera Corp. jkempa at altera dot com...
Pow -- --- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio news:3EA99B6A.132044DF@xilinx.com... > Powermos, > > The intial startup current peak occurs before configurat...
if your outputs are set to "outputs driving ground", you won't get much return current through the I/O buffer itself -- but the act of adding the via will reduce the size of inductive loops in the PCB via region, reducing your inductive coupling. Regards, Paul Leventis Altera Corp. ...
#A logic option that specifies the propagation delay from an input pin #to the data input of the input register implemented in the I/O cell #associated with the pin. This is an advanced option that should be #used only after you have compiled a project, checked the I/O timing, #and ...
>> Altera Corp. ReplyStart aNew Thread Reply byJohn Rible●February 17, 2005 Subroto- Tried it LATE last night. It works. And now the error message makes sense; is this difference from the Verilog LRM documented anywhere? Thank you, ...
> > Regards, > > Paul Leventis > Altera Corp. Thanks for your response. By this time I have fixed the problem that caused the original circuit not to work as supposed. There was some critical timing issue that caused a shift register a) not to load b) to load only certain flip-...