asicfpgaedaverilogcsrcommand-line-toolsystemveriloguvmregistersaxiambaapbregister-descriptionssystemrdl-compilerhardware-description-languageuvm-register-model UpdatedApr 23, 2025 Python lucky-wfw/ARM_AMBA_Design Star120 Code Issues Pull requests Based on ARM AMBA bus protocol, Verilog is used to design th...
PRADEEPCHANGAL / APB-Protocol-Verification-using-UVM Star 5 Code Issues Pull requests APB verification using UVM verification systemverilog apb systemverilog-test-bench apb-verification apb-verification-using-uvm apb-systemverilog Updated Aug 21, 2023 SystemVerilog Improve this page Add a desc...
AHB-APB UVM Verification Environment. Contribute to Gateway91/AHB-APB_Bridge_UVM_Env development by creating an account on GitHub.
Last commit message Last commit date Latest commit seabeam Update LICENSE Aug 24, 2020 58b7b6d·Aug 24, 2020 History 19 Commits .vscode include sim src/sv test LICENSE README.md README MIT license yuu_apb UVM APB VIP, part of AMBA3&AMBA4 features supported ...
task yuu_apb_master_driver::main_phase(uvm_phase phase); wait(vif.preset_n === 1'b1); @(vif.drv_cb); vif.wait_cycle(); fork forever begin get_and_drive(); @@ -79,6 +79,7 @@ task yuu_apb_master_driver::get_and_drive(); `uvm_do_callbacks(yuu_apb_master_driver, yuu_apb...
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP). - GitHub - courageheart/AMBA_APB_SRAM: AMBA v.3 APB v.1 Specifica
UVM Basics I am using this repository to practice UVM coding. The idea is to use a very simple design (APB memory in this case) and focus on the UVM side. I've tried to comment as much of the code as possible. I will keep adding whatever I think is interesting and what I might ...
class ahb_apb_vseq extends base_vseq; `uvm_object_utils(ahb_apb_vseq); ahb_reset_sequence ahb_reset_seq_h; ahb_main_sequence ahb_main_seq_h; ahb_slave0_sequence ahb_slave0_seq_h; ahb_slave1_sequence ahb_slave1_seq_h; ahb_slave2_sequence ahb_slave2_seq_h; ahb_slave3_sequence...
uvm_active_passive_enum is_active = UVM_ACTIVE; boolean coverage_enable = False; Expand All @@ -21,17 +23,19 @@ class yuu_apb_agent_config extends uvm_object; boolean protocol_check_enable = True; `uvm_object_utils_begin(yuu_apb_agent_config) `uvm_field_int(index, UVM_PRINT | UVM...
(uvm_phase phase); super.build_phase(phase); if(!uvm_config_db#(virtual apb_if)::get(this, "", "apb_intf", apb_vif)) `uvm_fatal("NO_VIF",{"virtual interface must be set for: ",get_full_name(),".apb_vif"}); if(!uvm_config_db#(int)::get(this,"*","device_id",slave...