The NC Drill Output (NC Drill Excellon format 2) will generate up to six different NC files for three different hole kinds and whether or not they are plated or non-plated. One of the most important procedures in creating a new component footprint is placing the pads that will...
•Platedand/ornon-platedholes. •Holesassociatedwithpads/viasthatarepartofacomponentand/orfree. •Allholetypes,oronlyround,squareorslottedholes. •Selectedand/orunselectedholes. •Onlythelayer-pairsofinterest. Oncethecriteriadefined,thepanellistsalluniqueholedefinitionsandsubsequentlythepadsand/orvias...
Design objects can be placed on any layer, however, the outline is normally created on the Top Overlay (silkscreen) layer and the pads on the multi-layer (for thru-hole component pins) or the top signal layer (for surface mount component pins). When you place the footprint on a PCB,...
non plated through holes. If the pin is metallic in the 3D model or specified in the notes that the pins are metallic, most likely they would need a plated through hole unless otherwise specified. You may have an non plated through hole for a metallic pin, but it has to be specified ...
and conductive planes. The mechanical structure is made up of the insulating material laminated between the layers of conductors. The overall structure is plated and covered with a non-conductive solder mask, and silk screen is printed on top of the solder mask to provide a legend for electronic...
2 Pads and vias with a hole size between 15and 30@2 焊盘和过孔的孔大小在15-30之间 2.2uF Capacitor@2.2uF 电容 4 All testpoints@4 全部测试点 4 Port Serial Interface@4 端口串行接口 4.7K Resistor@4.7K 电阻 47K Resistor@47K 电阻
(normal, blind, buried and total), num. pads with plated holes, num. pads with unplated holes, total num. holes, smallest and largest hole sizes, number of different hole sizes, smallest annular ring, minimum track width, number of copper layers, board width, board height, and board area...
•Platedand/ornon-platedholes. •Holesassociatedwithpads/viasthatarepartofacomponentand/orfree. •Allholetypes,oronlyround,squareorslottedholes. •Selectedand/orunselectedholes. •Onlythelayer-pairsofinterest. Oncethecriteriadefined,thepanellistsalluniqueholedefinitionsandsubsequentlythepadsand/or ...
2 Pads and vias with a hole size between 15and 30@2 焊盘和过孔的孔大小在15-30之间 2.2uF Capacitor@2.2uF 电容 4 All testpoints@4 全部测试点 4 Port Serial Interface@4 端口串行接口 4.7K Resistor@4.7K 电阻 47K Resistor@47K 电阻
This solution is acceptable in this situation because the only other component with thru-hole pads is the connector, which has pads spaced 1 mm apart. If this was not the case, the best solution would be to add a second clearance constraint targeting just the transistor pads, as was done ...