DMAC_FLAGS_CYCLIC|DMAC_FLAGS_TLAST);// enable circular mode Xil_Out32(VDMA_BASEADDR+DMAC_REG_SRC_ADDRESS, VIDEO_BASEADDR);// start address Xil_Out32((VDMA_BASEADDR+AXI_VDMA_REG_START_2), VIDEO_BASEADDR);// start address Xil_Out32((VDMA_BASEADDR+AXI_VDMA_REG_START_3), ...
65 + INCS += $(DRIVERS)/axi_core/axi_adc_core/axi_adc_core.h \ 66 + $(DRIVERS)/axi_core/axi_dac_core/axi_dac_core.h \ 67 + $(DRIVERS)/axi_core/axi_dmac/axi_dmac.h \ 68 + $(DRIVERS)/axi_core/jesd204/axi_jesd204_rx.h \ 69 + $(DRIVERS)/axi_core/jesd204/axi...
产品编号:ADRV9009-ZU11EG RF-SOM Hello, I'm working on a ADRV9009-ZU11EG RF-SOM. In my design I'm using two ADI AXI DMA Controller in cyclic mode to implement a DDR4 FIFO. APRODUCERDMA controller gets data from a s_axis source interface end writes the data out into the destinatio...
I use adi axi dmac receive data from ad9361 . but sometimes , when damc irq assert, the data in ps memory is out of order. for example , the order of data should be "A-B-C-D" , but in fact the order of data in memory is "A-C-B-D". data width of dmac is 256 bit , ...
adi axi dmac receive data out of order 类%E5%88%AB:Software 产品编号:adi axi dma 软件版本:1.0 Hello: I use adi axi dmac receive data from ad9361 . but sometimes , when damc irq assert, the data in ps memory is out of order. for example , the order of data should be "A-B-C...