1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-1 is used, it is referring to that specific member of the AD9522 family. Applications Low jitter, low phase noise clock distribution ...
中文数据手册 AD9522-1datasheet.pdf 产品信息 优势和特点 低相位噪声、锁相环(PLL) 片内VCO的调谐频率范围为2.27 GHz至2.65 GHz 支持最高2.4 GHz的外部3.3 V/5 V VCO/VCXO 1路差分或2路单端基准输入 支持最高250 MHz的CMOS、LVPECL或LVDS基准 基准输入接受16.62 MHz至33.3 MHz晶振 可选基准时钟倍频器 ...
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查Datasheet、查价格、查替代料 搜索一键BOM配单AD9522-1/PCBZ 厂商: AD(亚德诺) 封装: - 描述: BOARD EVAL FOR AD9522-1 CLK GEN 数据手册:下载AD9522-1/PCBZ.pdf立即购买 数据手册 价格&库存 AD9522-1/PCBZ 数据手册 切换侧栏 查找 上一页 下一页 / 16 演示模式打开当前在看 缩小 放大 Evaluati...
This configuration works fine when using the Eval Board. However, I am unable to get an clk output when using my design. At the most, I get a high level signal when I program an output channel in CMOS format. Using the STATUS pin, I have verified the following: ...