AD9516中文版资料和配置流程 AD9516_3 ---集成的2.0 GHz VCO的14路输出时钟发生器一、特征：①低相位噪声，锁相环（PLL）②片上VCO从1.75 GHz到2.25 GHz调谐 ③外部可选的VCO / VCXO 高达2.4 GHz ④1个差分或2个单端参考输入 ⑤接受LVPECL ，LVDS或CMOS 250 MHz的输出频率 ⑥6双1.6 GHz的LVPECL...
AD9516_17_18 Evaluation Software安装包及9516-3ARM配置程序 时钟芯片AD9516-3设计参考资料 上传者:qq_35859460时间:2022-06-08 ad9516.rar_FPGA寄存器_SPI FPGA_ad9516-3 fpga_ad9516默认配置 在FPGA上编写的通过SPI总线配置外部PLL芯片AD9516的程序,通过板级调试,验证可用。程序通过状态机实现,将需要配置的寄存...
AD9516_17_18 Evaluation Software.exe AD9516_17_18EvalSetup1.1.0.zip 使用步骤 软件界面如下: 输入你的参考时钟,我以我的自己的例子来讲解哈。 1 我使用了REF1=61.44Mhz,那么在REF1 中输入 61.44,并选择为输入(点击黄色块)。 2 配置N 分频和R 分频,这个要稍微计算下咯。
ZIP 4.37 M AD9516/AD9517/AD9518 Evaluation Software (Rev. 2.1.1) This installer contains USB drivers that are both 32- and 64-bit compatible. Note: Older AD9516/AD9517/AD9518 evaluation boards will need to have the USB controller EEPROM re-flashed in order to use this driver. ZIP 1.2...
Evaluation Software (3) Design Tool (1) Evaluation Software ZIP 4.37 M AD9516/AD9517/AD9518 Evaluation Software (Rev. 2.1.1) This installer contains USB drivers that are both 32- and 64-bit compatible. Note: Older AD9516/AD9517/AD9518 evaluation boards will need to have the USB cont...
evaluation software with simple graphical user interface On-board PLL loop filter Easy access to digital I/O and diagnostic signals via I/O header Status LEDs for diagnostic signals The AD9516-x, AD9517-x, and AD9518-x are very low noise PLL clock synthesizers featuring an integrated VCO, ...
8个交流耦合差分LVPECL SMA连接器 2个交流耦合LVPECL差分接头 2个直流耦合差分LVDS SMA连接器,可重新配置到四个CMOS SMA连接器 2个直流耦合LVDS差分接头,可重新配置到四个CMOS连接器 SMA连接器用于 2个参考输入 电荷泵输出 时钟分配输入 通过USB接口连接PC ...
Evaluation Software (3) Design Tool (1) Evaluation Software ZIP 4.37 M AD9516/AD9517/AD9518 Evaluation Software (Rev. 2.1.1) This installer contains USB drivers that are both 32- and 64-bit compatible. Note: Older AD9516/AD9517/AD9518 evaluation boards will need to have the USB cont...