int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis) 采样频率设置函数: /** * Set the TX sampling frequency. * @param phy The AD9361 current state structure. * @param sampling_freq_hz The desired frequency (Hz). * Example: * 30720000 (30.72 MHz) * ...
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config); ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config); //set fir param ad9361_set_tx_fir_en_dis(ad9361_phy, 0); ad9361_set_rx_fir_en_dis(ad9361_phy, 0); //set sample rate //ad9361_set_tx_sampling_freq(ad9361_phy, ...
int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz) Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired sampling frequency in Hz. Returns 0 in case of success, negative error code ...
tx_samp_freq=Sets the TX sampling frequency [Hz]. tx_rf_bandwidth?Gets current TX RF bandwidth [Hz]. tx_rf_bandwidth=Sets the TX RF bandwidth [Hz]. tx1_attenuation?Gets current TX1 attenuation [mdB]. tx1_attenuation=Sets the TX1 attenuation [mdB]. ...
Before starting the TX baseband filter tune, set this divider value using the following equation into registers 0x0D6 and 0x0D7. BBPLL _ Freq TXBBFDivide[8 : 0] min(511, ceiling ( )) 下载文档 收藏 分享 赏 0您可能关注的文档
A | Page 7 of 128 UG-570 AD9361 Reference Manual BBPLL VCO CALIBRATION The VCO calibration is run during the ad9361_set_rx_lo_freq The BBPLL VCO calibration must be run during initialization and ad9361_set_tx_lo_freq functions. First, set up any of the AD9361 device. This calibration...
TX tuner block Before starting the TX baseband filter tune set this divider value using the following equation into registers 0 x0D6 and 0 x0D7 511min 0 8 TXTuneCLK fDesired FreqBBPLL ceilingeTXBBFDivid Typical Sequence 1 Follow the order of events in the scripts generated by the AD...
In Step 1.4, set the DUT synthesis frequency. The DUT synthesis frequency depends on the baseband sampling rate of the system. The MIB Recovery algorithm implementation in this example is built for a sampling rate value of 61.44 MHz. Step 2 prepares the model for HDL code generation by perfor...
3451 + uint32_t *tx_path_clks); 3437 3452 uint32_t ad9361_to_clk(64_t freq); 3438 3453 uint64t ad9361_from_clk(uint32_t freq) 3439 3454 int32_t ad9361_read_rssi(struct ad9361rf_phy *phy, struct rf_rssi *rssi); 3440 3455 int_t ad9361_set_gain_ctrl_mode(...
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