//ad9361_set_rx_sampling_freq(ad9361_phy, 10000000); //set lo //ad9361_set_tx_lo_freq(ad9361_phy, 2400e6); //ad9361_set_rx_lo_freq(ad9361_phy, 2400e6); //set bandwidth //ad9361_set_tx_rf_bandwidth(ad9361_phy, 18000000); //ad9361_set_rx_rf_bandwidth(ad9361_phy, 18000000...
int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz) 设置射频载波频率: /** * Set the TX LO frequency. * @param phy The AD9361 current state structure. * @param lo_freq_hz The desired frequency (Hz). * Example: * 2400000000 (2.4 GHz) * ...
int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy, uint32_t sampling_freq_hz) Sets the sampling frequency. Receives as parameters a structure that contains the AD9361 current state and the desired sampling frequency in Hz. Returns 0 in case of success, negative error code ...
rx_samp_freq=Sets the RX sampling frequency [Hz]. rx_rf_bandwidth?Gets current RX RF bandwidth [Hz]. rx_rf_bandwidth=Sets the RX RF bandwidth [Hz]. rx1_gc_mode?Gets current RX1 GC mode. rx1_gc_mode=Sets the RX1 GC mode.
1.4 * BBBW * 2π Desired _ f RXTuneCLK ln(2) To generate this RXTuneCLK, the BBPLL is divided down using a divide by 1 to 511 divider dedicated to the RX tuner block. Before starting the RX baseband filter tune, set this divider value using the following equation. BBPLL _ Freq RX...
A | Page 7 of 128 UG-570 AD9361 Reference Manual BBPLL VCO CALIBRATION The VCO calibration is run during the ad9361_set_rx_lo_freq The BBPLL VCO calibration must be run during initialization and ad9361_set_tx_lo_freq functions. First, set up any of the AD9361 device. This calibration...
RXTuneCLK the BBPLL is divided down using a divide by 1 to 511 divider dedicated to the RX tuner block Before starting the RX baseband filter tune set this divider value using the following equation 511min 0 8 RXTuneCLK fDesired FreqBBPLL ceilingeRXBBFDivid Typical Sequence 1 Follow the ...
In Step 1.4, set the DUT synthesis frequency. The DUT synthesis frequency depends on the baseband sampling rate of the system. The MIB Recovery algorithm implementation in this example is built for a sampling rate value of 61.44 MHz. Step 2 prepares the model for HDL code generation by perfor...
LICENSE README.md UPDATE.BAT cal_ad9361.c example_pluto.py makefile pluto.py pluto_ramboot pluto_temp.sh pluto_triangle.py pluto_tx_data.py plutosdr_sweepTXLO power.c power_check.c runme0.sh ssh_config sshanalog update update_ip ...
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