1_TX_LO_fastlock_load -rw-r--r-- 1 root root 4096 Jan 15 13:49 out_altvoltage1_TX_LO_fastlock_recall -rw-r--r-- 1 root root 4096 Jan 15 13:49 out_altvoltage1_TX_LO_fastlock_save -rw-r--r-- 1 root root 4096 Jan 15 13:49 out_altvoltage1_TX_LO_fastlock_store -rw...
When in fastlock pin select mode (adi,[tx|rx]-fastlock-pincontrol-enable). This file needs to be written once with a value, before the pin-control can be used. This will moves the device into fastlock mode. This specifies any shell prompt running on the target ...
ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile); 3490 - intt ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile); 3507 + intt ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, 3508 + int32_t arg...
AD9361 fast lock模式下快速校准VCO ,TX发射出的频点偏移了一点,请问原因可能是什么? 标签:VCOFDDAD936165391 5 2 AD9361镜像干扰和谐波干扰 请问是什么原因? 标签:CMOSDDSAD936192145 2 0 请问谁有AD9361 Evaluation software 标签:AD936134512 3 0
adi,tx-fastlock-delay-nstx_fastlock_delay_nsTX fastlock delay inns adi,rx-fastlock-delay-nsrx_fastlock_delay_nsRX fastlock delay inns adi,rx-fastlock-pincontrol-enablerx_fastlock_pincontrol_enableRX fastlock pin control enable adi,tx-fastlock-pincontrol-enabletx_fastlock_pincontrol_enableRX...
Fast Lock Initial Wider BW Option ... 22 Configuring and Using a Fast Lock Profile... 23 Fast Lock Pin Select ... 24 Enable State Machine Guide ... 25 Overview ...
Rx Fast Lock Registers (Address 0x25A Through Address 0x25F) ... 64 Rx LO Generation Register (Address 0x261) ... 65 Tx Synthesizer Registers (Address 0x270 Through Address 0x291) ... 65 DCXO Registers (Address 0x292 Through
Fast Lock Profiles 22 Overview 6 Overview 22 Initalization Calibrations 7 Fast Lock Initial Wider BW Option 22 BBPLL VCO Calibration 8 Configuring and Using a Fast Lock Profile 23 RF Synthesizer Charge Pump Calibration 8 Fast Lock Pin Select 24 RF Synthesizer VCO Calibration 8 Enable State ...
This register specifies the fast AGC lock level or specifies the slow AGC inner high threshold. Resolution is ?1 dBFS/LSB. SPI Register 0x0FC—AGC Config 3 [D7:D5]—Manual (CTRL_IN) Incr Gain Step Size[2:0] Applies to MGC and if the CTRL_IN signals control gain (0x0FB[D1:D0...
Fixed hard-lock caused by EHCI SMI in OpenDuetPkg Added preview UEFI Secure Boot compatibility Added FuzzyMatch option to support fuzzy kernelcache matching on 10.6 and earlier Added KernelArch option to specify architecture preference on older kernels Added KernelCache option to specify kerne...