另外,还可以对输入时钟进行延时调节或者通过SelectIO的delay、delayctrl功能对时钟信号进行微调,以满足时序要求。 芯片数据时钟与数据之间的时序可靠性也可以通过芯片内部的延时寄存器0x006、0x007进行条件,以此达到要求,具体的SPI配置寄存器时序如图 3 AD9361 寄存器配置接口SPI时序所示。此方面不是本文重点,不做展开,更多...
另外,还可以对输入时钟进行延时调节或者通过SelectIO的delay、delayctrl功能对时钟信号进行微调,以满足时序要求。 芯片数据时钟与数据之间的时序可靠性也可以通过芯片内部的延时寄存器0x006、0x007进行条件,以此达到要求,具体的SPI配置寄存器时序如图 3 AD9361 寄存器配置接口SPI时序所示。此方面不是本文重点,不做展开,更多...
AD9361辅助ADCDAC通常接口温度传感器
An over-range occurrence in the RX FIR filter is indicated in registers 0x05E and 0x05F or at the CTRL_OUT pins when the control output pointer in register 0x035 is set to 0x0A. All adjustable RX filter settings are programmable via SPI registers....
adi,mgc-dec-gain-stepmgc_dec_gain_stepThis attribute applies if the CTRL_IN signals control gain. The gain index decreases by this value when certain CTRL_IN signals transition high. See register 0x0FE, bits [D7:D5]. This data is processed by the driver. ...
hybridThe AGC hybrid mode is the same as the slow AGC mode with the exception that the gain update counter is not used. Instead, gain updates occur when the BBP pulls the CTRL_IN2 signal high. The “hybrid” term arises because the BBP has taken some control of the algorithm away from...
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? ? P1_D[11:0] P0_D[11:0] DATA_CLK FB_CLK RX_FRAME TX_FRAME 2 8 TXNRX AUX_DAC ENABLE TX EN_AGC RX CTRL_OUT TX_MON CTRL_IN GPO SPI_ENB SPI_CLK SPI_DI SPI_DO SYNC_IN 12 12 2 2 2 2 RF FRONT END 12 2 4 8 4 BBP CLK_OUT PLL XTAL_N XTAL_P AD9361 Figure 1: ...
In the signal description the pins are: CTRL_IN2 = pin D5 CTRL_IN3 = pin D6 In the package drawing the pins are: CTRL_IN2 = pin D6 CTRL_IN3 = pin D5 I currently assume that the package drawing is accurate. What is correct?
In FMCOMMS5 with ZCU102, ad9361_master is connect to HP Bank 66 and ad9361_slave is connected to HP bank 65, while the ctrl_in and ctrl_out GPIOs of these both ad9361 ICs are connected to HP bank 67. So I have moved the ctrl_in and ctrl_out GPIOs from HP ban...