Hello, Yes, you can do that. I think you're referring to the minimum center frequency from this table: Please take note of the specific conditions under which 12MHz is the minimum frequency. This is not the absolute minimum frequency that the device support...
https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1135770/cd74hct7046a-can-this-ic-be-used-to-detect-lock-a-frequency-of-107-khz 器件型号:CD74HCT7046A 主题中讨论的其他器件:CD74HC7046A CD74HC7046A/CD74HCT7046A 的数据表提到了12MHz 的最小中心频率。 它还提到"...
Voltage-to-Frequency Conversion Motor-Speed Control Related Literature AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046ACD74HC7046A的参数(英文): Technology Family HC Bits (#) 1 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type ...
The 74HC/HCT7046 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC= 4.5 V • Choice of two phase comparators: EXCLUSIVE-OR; edge-triggered JK flip-flop;...
The 74HC/HCT7046 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC= 4.5 V • Choice of two phase comparators: EXCLUSIVE-OR; edge-triggered JK flip-flop;...
High impedance in wide frequency range due to divided bobbin Operating temperature range from -25°C to +120°C Low leakage magnetic flux to outside Compact size and low height UL94 V-0 flame retardant rated base and bobbin Technical Specifications Find similar products Inductance 4.6...
be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency. The phase comparator gain is: V CC r). ...
and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz...
Excellent VCO Frequency Linearity VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption Minimal Frequency Drift Zero Voltage Offset Due to Op-Amp Buffer Operating Power-Supply Voltage Range VCO Section...3V to 6V Digital Section...2V to 6V ...
shortens instrument set-up time. At the press of a button, the parameters rele- vant for display, e.g. center frequency,span and level range, are adjusted to the applied signal; for a pulsed s ignal,the gate sweep parameters are also adjusted. For standard compliant mea- surements ...