Rad-hard flip-flopSingle event upsetThe DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This pa
However, while FF-TMR uses three simple FFs and a voter (and therefore in principle could be implemented in RTL) as a redundant cell, FFD-TMR and other designs require technology-specific adjustment at layout and electrical level within the sequential element. For instance, the DICE-FF ...
The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the ...
Flip flopMultiple node upsetradiationThis paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop ...
flip-floplow-powerradiation-hard designIn this paper, we propose a low-power area-efficient redundant flip-flop for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves ...
Rennie "Neutron- and proton-induced single event upsets for D- and DICE-flip/flop designs at a 40 nm technology node", IEEE Trans. Nucl. Sci. , vol. 58, no. 3, pp.1008 -1014 2011T. D. Loveless,S. Jagannathan,T. Reece.Neutron- and Proton-Induced Single Event ...
DICE-TYPE COUPLINGSFIELD-EFFECT HETEROTRANSISTORSOPTIMIZATION OF MANUFACTURINGIn this paper we introduce an approach to increase integration rate of field-effect transistors framework a single-bit CMOS two-phase RS flip-flop with DICE-type couplings. Framework the approach we consider manufacturing the ...