These devices are cascode-connected normally-on SiC JFETs, which have a normally-off functionality. The drain and source terminals of each JFET were connected together for this test. TR1 was signalled on and off, and TR2 was signalled on at a duty cycle of 100%. Waveforms are shown in ...
1. CMOS is integrated with complementary JFETs. 2. In one embodiment, CMOS is built without any “spacer”. 3. Contacts to the CMOS terminals can be planar, or at the same level, which can improve the manufacturability of the devices. 4. Other salient features of exemplary CMOS devic...
The phase-shifted full-bridge is coupled to primary terminals Tp1, . . . , Tpm of the matrix integrated magnetic device and the current multiplier rectifier is coupled to secondary terminals Ts1, . . . , Tsm of the matrix integrated magnetic device. Stated another way, primary windings (...
In [26], three methods of Miller effect crosstalk suppression for Si devices are stated: (1) add additional capacitance between gate–source terminals to shunt the Miller current, (2) apply a negative-biased turn-OFF gate voltage, and (3) active Miller clamping. However, due to the ...