It is composed of an Analog Front-End (AFE), an Analog-to-Digital Converter (ADC) and a Digital Back-End (DBE). The TDC’s input signal is temperature; the AFE, the first block of the chain, is responsible to sense it achieving an electrical form for it (either in the voltage or...
Depending on the temperature sensing device, CMOS temperature sensors can be divided into BJT-type, resistor-type, full MOS transistor-type, and thermal diffusivity (TD) -type [4,5,6,7]. Based on the current mainstream architecture, on-chip integrated CMOS temperature sensors can be roughly ...
M. H. Perrott et al., "A temperature-to-digital converter for a MEMS-based programmable oscillator with frequency stability and integrated jitter," IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 276-291, Jan. 2013.M. H. Perrott et al., "A Temperature-to-Digital Converter for ...
A Time-to-Digital Converter with 35 ps Resolution and 2.5 ?s Range A time-to-digital converter (TDC) with 50 ps LSB and 2.5 ?s measurement range has been implemented in a 0.8 ?m BiCMOS process. The TDC is based on a main counter and two separate time digitizers for interpolation ...
The time measurement is performed inside each pixel by a Time to Digital Converter (TDC) based on time to amplitude conversion. The development is part of the R&D activity for the beam spectrometer, called Gigatracker (GTK), of the NA62 Experiment at CERN. 展开 ...
A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch...
A 16-bit high-speed digital-to-analog converter is presented. The device is a high-performance digital/analog mixed-signal circuit. Operating at ±5 V, the circuit has a conversion rate higher than 30 MSPS and a settling time of 50 ns. Fabricated with a 2-μm BiCMOS technology, the D...
System clock optimization can be both challenging and rewarding. It may be relatively easy to design an analog-to-digital converterencodecircuit with a respectable 350 femtoseconds (fs) of jitter, but is this adequate for today’s high speed requirements? For example, when testing anAD9446-100...
This paper introduces a digital multi-mode boost converter with wide range of input voltage for an energy recycling load system. The boost converter is controlled digitally with constant off- time/constant frequency hybrid pulse width modulation (PWM) control. Constant off-time control is to avoid...
Abstract This paper reports the design of a 10-bit, high-resolution time-to-digital converter (TDC) based on Vernier residues amplification which is a novelty. This TDC architecture allows the measurement of wide time intervals with high picosecond-range resolution. The key benefits of the propose...