Typically, precision SAR ADCs [3], [4], which are generally defined at 16-bit and greater, sample at below a few MS/s. A few works [1], [2] have pushed the speed further. They use 2-bit/trial and the pipelined SAR architecture [7], [10] to speed up the operation, at the...
A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS 2017 Symposium on VLSI Circuits (2017) Google Scholar [11] J. Shen, et al. A 16-bit 16-MS/s SAR ADC with On-Chip Calibration in 55-nm CMOS IEEE J. Solid State Circ., 53 (4) (2018), pp. 1149-1160 CrossrefVie...
A 10 b 50 MS/s 820 W SAR ADC with on-chip digital calibration. IEEE ISSCC Dig Tech Papers, 2010: 384M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamono, "A 10-b 50-MS/s 820- W SAR ADC with on-chip digital calibration," in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, ...
This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a...
9.2: A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm 9.3: A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs 9.4: A 182.3dB FoMs 50MS/s ...
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precisio...
–40°C to +125°C • Package: 64-Pin LQFP 3 Description The ADS8584S device is an 4-channel, integrated data acquisition (DAQ) system based on a simultaneous-sampling, 16-bit successive approximation (SAR) analog-to-digital converter (ADC) operating at a maximum of 330 kSPS per channe...
报告题目:A Three-wafer-stacked, Hybrid 15MP CIS + 1 MP EVS with 4.6 GEPS Readout, In-pixel TDC and On-chip ISP and ESP Function 郭啸峰,纽瑞芯 Xiaofeng Guo , NewRadio Technologies Co., Ltd. 报告题目:A 13b 600-675MS/s Tri-State Pipelined-SAR ADC with Inverter...
A 12-bit low power SAR A/D converter with medium speed is designed,which can work under a 5 V power supply.A charge scaling D/A converter with capacitor voltage divider is designed,which extends the resolution of a parallel D/A converter as well as reduces the chip area.Built-in 3.3V...
The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038mm2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step....