This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compe...
A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with red... Y Zh...
这里多说一点,该论文使用的pre-amp是五管运放结构,高精度SAR ADC一般使用的OP都是折叠式高增益大带宽的,所以T_pre_amp的取值跟小信号和大信号的相应速度都用关系,前面数十个比较周期主要跟大信号有关,最后几位的比较则跟小信号的响应相关。 为了提高比较器的性能(噪声的角度),一般输入对管的过驱动电压设置不会...
A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed in this paper. The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hy...
the digital logic in the SAR ADC improves with CMOS process scaling. SAR ADCs have achieved sampling rates from several tens of MS/s to low GS/s with 10-bit resolution [4], [5], [6]. SAR-assisted pipelined ADCs [7] have achieved good power efficiency at speeds exceeding 200MS/s. ...
Fabricated in 65-nm CMOS with an active area of 0.06 mm2, it achieves a peak SNDR of 55.1 dB and a peak SFDR of 71.5 dB at 40 MS/s sampling rate. The power consumption is 1.21 mW. 展开 关键词: Analog-to-digital converter (ADC) area efficient pipelined SAR single-ended successive ...
A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS Shen, S. Decker, H. Li, E. Ibaragi, "A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. ... Kapusta,R.,Shen,... - 《IEEE Journal of Solid State Circuits》 被引...
The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/...
A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register(SAR)analog-to-digital converter(ADC) in 65 nm CMOS process with ... Lu, Yuxiao,Sun, Lu,Li, Zhe,... - 《Journal of Semiconductors》 被...
摘要原文 In this work a low power SAR ADC with 8.9 ENOB for wireless communication systems is presented. A capacitive charge redistribution DAC with a unit capacitor of 0.5fF is used. The implemented charge-sharing technique, allows the use of 2^(N-1) + 1 unit capacitors, instead of the...