This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compe...
dsPIC33/PIC24 12位高速多SAR模数转换器(Analog-to-Digital Converter,ADC)包含以下特性: • 多个ADC内核: - 多个单通道专用ADC内核(取决于具体器件实现) - 一个共用ADC内核 • 每个ADC内核可配置为6、8、10或12位分辨率 • 12位分辨率时,每通道的转换速率最高为3.25 Msps • 最多32个模拟输入源(...
This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mWfrom 1 V supply, and occupies 0.57 mm(2) in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even ...
IP_数据表(A-13):12bit 2MSps SAR ADC(R06PM0013EJ0111) 2023-03-14 0次下载 下载 LTC2262-12:12位、150Msps超低功耗1.8V ADC数据表 2021-05-24 9次下载 下载 LTC2380-16:16位、2Msps、低功耗SAR ADC,带96.2dB SNR数据表 2021-05-22 6次下载 下载 24位2Msps SAR ADC 2021-05-20 ...
摘要: A new redundant successive approximation register (SAR) ADC architecture with digital error correction is presented to avoid the comparator offset issue and subtraction operations. A 2-channel 12-bit...关键词: Analog-to-digital converter Successive approximation Pipeline Time-interleaved Digital ...
bit flash blocks other than the flash comparators, operates at 3.3 V to accommodate traditional precision applications, the rest of the circuits all operate under 1.2 V supply. The digital engine includes bit weight calibration and data reconstruction. The ADC operates in two modes, illustrated ...
bit flash blocks other than the flash comparators, operates at 3.3 V to accommodate traditional precision applications, the rest of the circuits all operate under 1.2 V supply. The digital engine includes bit weight calibration and data reconstruction. The ADC operates in two modes, illustrated ...
The first stage design of a SHA-less 12-bit 200-Ms/s pipeline ADC in 130-nm CMOS A first stage of a SHA-less 12-bit 200 MSps pipeline analog-to-digital converter (ADC) is designed in this paper. A high speed and high precision comparato... Y Yin,X Jiang,H Deng - IEEE Internati...
IP_数据表(A-14):12bit 2.5MSps SAR ADC消耗积分:0 | 格式:pdf | 大小:141.85KB | 2023-07-06 吴湛 9年用户 分享资料780个 关注 IP_Datasheet(A-14):12bit 2.5MSps SAR ADC 瑞萨 下载并关注上传者 开通VIP,低至0.08元下载/次 下载资料需要登录,并消耗一定积分。 声明:本文内容及配图由入驻...
Yang Siyu,Zhang Hui,Fu Wenhui,Yi Ting, and Hong Zhiliang State Key Laboratory of ASIC and System,Fudan University,Shanghai 201203,China,.A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator.[J];Journal of Semiconductors,2011-03...