A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f/sub s/=40 MHz fr... I Mehr,L Singer - Solid-State Circuits, IEEE Journal of 被引量: ...
A. Verma and B. Razavi, "A 10-Bit 500-MS/s 55-mW CMOS ADC," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009.S.-H. W. Chiang, H. Sun, and B. Razavi, "A 10-bit 800-MHz 19-mW CMOS ADC," IEEE J. Solid-State Circuits, vol. 49, no. 4,...
A 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDAC) and a fine-stage MDAC. The opamps for...
A 10-bit 10-MS/s reference-free SAR ADC in 90nm CMOS IEEE J. Solid-State Circuits (2010) S.M.Louwsmaet al. A 1.35GS/s, 10b, 175mW time-interleaved ad converter in 0.13μm CMOS IEEE J. Solid-State Circuits (2008) B. Verbruggen, M. Iriguchi, J. Craninckx, A 1.7mW 11b 25...
CMOS低功耗Based on 65 nm CMOS low leakage process, an 8-channel 10-bit 200 kS/s SAR (Successive Approximation Register) ADC (Analog-to-Digital Converter) IP core for touch screen SoC is realized. In the D/A converter design, a "7MSB (Most-Significant-Bit)-plus-3LSB (Least-Significant...
A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos 来自 掌桥科研 喜欢 0 阅读量: 77 作者:MZ Straayer,MH Perrott 摘要: A combined 5-bit, 1order noise-shaped quantizer and DEM circuit running at 950MHz based on a ...
The ADC is based on a 2.5-2.5-2.5-4 bits-per-stage pipeline architecture and occupies an area of 1.3 mmin a 0.35 mum CMOS process. At the target sampling rate of 20.48 MS/s, measured results show that the converter consumes 19.5 mW from a 1.5 V power supply and achieves 56 dB SNR ...
32-bit Arm® Cortex®-M3 Core, up to 60 MHz clock frequency 256 kByte flash memory 32 kByte Boot ROM memory (used for device firmware) 31 kByte RAM memory + 1 kByte secure RAM memory Harvard architecture Thumb®-2 Instruction set and hardware ...
DC1796A-E 电子元件开发板DEMO BOARD SAR ADC 18BIT 1.6MSPS 原厂 200 原厂 -- ￥1695.0000元1~-- 件 深圳市天熠电子科技有限公司 2年 -- 立即订购 查看电话 QQ联系 原装CY8C4125AZI-M43332-bit MCU 通用 电子材料电子元器件 1 -- ...
A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an ...