This paper describes a 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-/spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include operation on a 3.3 V power supply, optim...
R. Gray, “A 10 b, 20 Msample/s 35mW pipeline A/D converter.” IEEE J. Solid-State Circuits 30(3), 1995. A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC.” IEEE J. Solid-State Circuits 28(12), pp. 1207...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1044发...
Gray A 10-bit, 20-MS/s, 35-mw pipeline a/d converter 1994 Proceedings of IEEE Custom Integrated Circuits Conference (CICC), IEEE (1994), pp. 499-502, 10.1109/CICC.1994.379674 Google Scholar 61. W. Jung, et al. An ultra-low power fully integrated energy harvester based on self-...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1045...
Gray, “A 10b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, 1995. Google Scholar P. Favrat, P. Deval, and M.J. Declercq, “A high-efficiency CMOS voltage doubler.” IEEE J. Solid-State Circuits, vol. 33, ...
Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline A/D converter is presented in this paper. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dyn...
Data Sheet 12-Bit, 20 MSPS/40 MSPS/65 MSPS, Dual A/D Converter AD9238 FEATURES Integrated dual 12-bit ADC Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dB (to Nyquist, AD9238-65) SFDR = 80.5 dBc (to Nyquist, AD9238-65) Low power: 300 mW/channel at 65 MSPS ...
A 10-bit 100-MS/s 50 mW CMOS A/D converter pipeline processing0.18 micron1.8 V10 bit100 MHzA high-speed and low-power pipelined analog-to-digital converter was designed and simulated with a 0.18 ... Z Tao,M Keramat - IEEE International Symposium on Circuits & Systems 被引量: 20发表:...
Data Sheet 12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter AD9237 FEATURES Ultralow power 85 mW at 20 MSPS 135 mW at 40 MSPS 190 mW at 65 MSPS SNR = 66 dBc to Nyquist at 65 MSPS SFDR = 80 dBc to Nyquist at 65 MSPS DNL = ±0.7 LSB Differential input with ...