This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use ...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1047发...
长度 10 mm 湿度敏感性 Yes ADC 输入端数量 1 Input 转换器数量 1 Converter 工作电源电压 5 V Pd-功率耗散 330 mW 功耗 285 mW 参考类型 External, Internal 采样和保持 Yes 电源电压-最大 5 V 电源电压-最小 S/H ADC 宽度 498.600 mg 可售卖地 全国 型号 AD9240ASZ 产品...
Online project hosting using Git. Includes source-code browser, in-line editing, wikis, and ticketing. Free for public open-source code. Commercial closed source ...
Gray A 10-bit, 20-MS/s, 35-mw pipeline a/d converter 1994 Proceedings of IEEE Custom Integrated Circuits Conference (CICC), IEEE (1994), pp. 499-502, 10.1109/CICC.1994.379674 Google Scholar 61. W. Jung, et al. An ultra-low power fully integrated energy harvester based on self-...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1047发...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1044发...
Allstot, “An 85-mW, 10-b, 40-MSample/s CMOS parallel-pipelined ADC.” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 173–183, 1995. Article Google Scholar T.B. Cho and P.R. Gray, “A 10-b, 20-MSamples/s, 35 mW pipeline A/D converter.” IEEE J. Solid-State ...
HMCAD1104 v00.1111 Octal 10-Bit 20/40/50/65 MSPS A/D Converter Features • 65 MSPS Maximum Sampling Rate • Ultra Low Power Dissipation 12 mW/Channel at 20MSPS 20 mW/Channel at 40MSPS 25 mW/Channel at 50MSPS 30 mW/Channel at 65MSPS • 61.6 dB SNR at 8 MHz FIN • 0.5 ...
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW a... TB Cho,Gray, P.R - IEEE J. Solid-State Circuits 被引量: 1047发...